1. Field of the Invention
The invention relates generally to the field of electronic amplifiers and particularly to differential amplifiers used for sensing the binary logic state of a static electronic memory cell.
2. Prior Art
Semiconductor Random Access Memories (RAM's) of the type having a plurality of substantially identical memory cells can be broadly classified as either static or dynamic depending on the amount of D.C. power they dissipate during operation. Dynamic memories are generally low-power devices which store small quantities of the charge representative of binary information on capacitances. These small quantities of charge continually dissipate and must be periodically refreshed. Therefore, dynamic memories typically require special external clocking and refresh circuitry which is both complicated and expensive for a designer to incorporate in a digital system. Additionally, the output signals from these memories are often not compatible with standard transistor-transistor logic (TTL) levels and external interface circuits must be used where such compatibility is required.
Static memories continually dissipate D.C. power. In these memories, binary information is typically stored in a bistable flip-flop circuit in each memory cell. Each flip-flop circuit is securely latched in a selected operating mode corresponding to a given binary state by the continuous flow of a small current through each memory cell. Static memories may be either slow or fast depending on their architecture and the techniques used in their fabrication; however, they generally do not require any special clocking circuitry or refresh means and many of them have inputs and outputs which are compatible with standard TTL logic levels. Therefore, static memories are generally easier for a designer to incorporate in digital applications such as computer terminals and perpherials.
Static electronic memories are manufactured in integrated circuit form using various competing microelectronic technologies to obtain trade offs in operating speed, cost, and power consumption. N-channel silicon gate Metal Oxide Semiconductor (MOS) technology is particularily attractive from the standpoint of cost and power consumption. The access speed of static MOS RAM's is somewhat slower than access speed achievable using other technologies such as bi-polar Emitter Coupled Logic (ECL).
Among the many factors which influence the access speed of static MOS RAM's is the design of the sense amplifier used to detect the differential output signals from a memory cell. The differential output signals from a memory cell are selectively connectable to a pair of column bit lines which are selectively connectable to the sense amplifier. The differential signals on such column bit lines are typically 5.0 volts and 2.5 volts. When one of the bit lines is at 5.0 volts, and other is at 2.5 volts. Thus, the two binary states correspond to the two possible signal configurations. These signals levels (i.e., one high; generally the power supply voltage, and one intermediate voltage) are not compatible with standard MOS digital levels (i.e., one high; generally the power supply voltage, and one low, some voltage less than the threshold voltage for an enhancement mode MOS device.) Therefore, the sense amplifier must detect the logic state represented by the differential voltages and translate this information to standard MOS digital signal levels. Historically, it has been a difficult task to efficiently implement this translation.
Prior art static MOS RAM's have utilized differential Schmidt trigger circuits in their sense amplifiers. The Schmidt trigger design works, but suffers from a number of shortcomings. For example, when the circuit is designed to have the appropriate MOS digital level output signals, the input signal differential required to cause the trigger to change its output state is at least two volts. If the circuit was responsive to smaller input voltage differentials, then the speed of the trigger would be increased. Another problem associated with differential Schmidt triggers used in static MOS RAM sense amplifiers is that the time required for the circuit to charge the output line from a low signal level to a high signal level is inherently longer than the time required to discharge the output line from a high signal level to a low signal level. Unfortunately, no matter how fast the output line discharge rate, the useful speed of the circuit is limited by the slower output line charging rate. Both the output line charging rate and the minimum voltage differential required to cause the trigger to change its output state are dependent upon the threshold voltages of the transistors which comprise the trigger circuit. Because the transistor threshold voltage are dependent on process parameter variations, the actual access times of static MOS RAM's vary greatly from run to run and wafer to wafer.